1. Field of the Invention
The present invention relates to a static random access memory (SRAM) cell and a method for forming the same, and more particularly to a high load resistance (HLR) type SRAM cell.
2. Description of the Prior Art
As shown in FIG. 1, an SRAM cell includes six elements, a pair of driver transistors M1 and M2, a pair of load elements 10 and 10', and a pair of access transistors M3 and M4. The driver transistors M1 and M2 have the gates and drain electrodes cross-coupled, and the load elements 10 and 10' are connected to the drain electrodes of the driver transistors M1 and M2. Also, the access transistors M3 and M4 are connected to the drain electrodes of the driver transistors M1 and M2. The access transistors are controlled by the word line and connect the cell node to the bit line in order to control the access path of the cell.
The SRAM cell is classified into two classes by the type of the load elements , one of which is the thin film transistor (TFT) type SRAM cell and the other is the high load resistance (HLR) type SRAM cell. Typically, the TFT type SRAM cell has low power dissipation and is more profitable than the HLR type in the device integration. However, the manufacturing process of the TFT type SRAM cell is more complicated. Also, the TFT type SRAM cell has problems such as a low repeatability and a degradation of electrical characteristics in testing the reliability of the device. Therefore, a TFT type SRAM cell is used only for a low speed SRAM cell, and the HLR type SRAM cell, which is less restricted in the power dissipation, is used for a high speed SRAM cell.
The conventional HLR type SRAM cell has two polysilicon layers and two metal layers. That is, the gate of the driver transistor and the ground line are formed with a first conductivity layer, and the high load resistance and the power line are formed with a second conductivity layer.
However, in case the gate of the driver transistor and the ground line are formed with the same conductivity layer, the space between the gate of the driver transistor and the ground line must meet the design rule. For example, the space must be more than 0.6 .infin.m for a 4M SRAM. Therefore, the size of the cell may increase according to the space between the gate of the driver transistor and the ground line.
Moreover, it is not easy to convert a TFT type SRAM cell into a HLR type SRAM cell.